| تاریخ ارسال: 1400/8/30 |
Title: "The 3-D Interconnect Landscape"
3D integration technologies enable increasing complexity, reducing cost and adding new system functionalities to electronics products making sure that Moore's Law is continuing beside transistor gate length scaling. The goal of 3D integration is to improve the CMOS PPAC (power, performance, area and cost) aspects by smart partitioning, combining different technologies, different substrates and different functionalities all in one single chip. In this presentation the roadmap of advanced 3D packaging technologies will be reviewed with more details.
Dr. Jaber Derakhshandeh received the bachelor's, master and Ph.D. degrees all in electrical engineering f Tabriz, Sharif and Tehran universities, respectively. In 2006 he joined TU Delft electrical engineering department working on 3DIC, TFTs, CNTs, CMOS image sensors, electron, and X-ray detectors. In 2013, he joined 3D syst integration group at imec, where he is conducting research on exploratory projects on W2W (wafer to wafer) and D2W (die-to-wafer) stacking for high-density interconnections and quantum computers.
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