Abstract: High-speed serial and optical I/Os are driven continuously to higher density and bandwidth to enable the scaling of data centers to meet the demand imposed by a digitally connected world. The DSP based wireline and optical transceivers rely on high baud-rate data converters to transmit and receive the data. These data converters rely on high frequency, low jitter clocks to sample the data. This talk covers the requirements of a high-speed clock generation and distribution for data converters used in high-speed serial and optical I/Os and the latest design techniques to generate them with low power consumption to meet the stringent requirements of data-center interconnect.

Mahdi Parvizi received his Ph.D. degree in Electrical Engineering at McGill University, Montreal, QC, Canada. In ۲۰۱۲ he joined Ciena Corporation, Ottawa, ON, Canada, to work on Analog/Mixed Signal Circuit and Silicon Photonic Design for optical communications. In ۲۰۲۱ he joined Acacia as a Principal Millimeter-Wave and Mixed-signal Architect. Since the acquisition of Acacia by Cisco, he is a technical lead at Cisco. Furthermore, he has been an Adjunct Research Professor in Electronics department at Carleton University, Ottawa, ON, Canada, Since ۲۰۱۸. His area of expertise includes low power CMOS wireline transceivers, high-speed data-converters, high-speed TIA/drivers, low-power clocking solutions for wireline/optical transceivers, Si-photonic modulators, and ultra-low power and ultra-low voltage circuits for wireless sensor network applications.
Mahdi Parvizi received ISSCC ۲۰۱۲ Student Research Preview Best Paper Award for “An Ultra-Low Power, Low Voltage, Wideband CMOS LNA with Partial Noise and Distortion Cancellation”. Dr. Parvizi has authored or co-authored more than ۲۵ conferences and journal papers and ۱ book chapter. He holds sixteen patents in the field of circuit design for wireline and optical communications.